1. Field of the Invention
The present invention relates to a signal transmission circuit having a plurality of input terminals and a common output terminal for transmitting an input signal pulse without deformation of the inputted signal pulse profile. Particularly, it relates to a simplified signal transmission circuit for a semiconductor storage device for comparing an output of a storage cell with that of a reference cell.
2. Description of the Prior Art
With the rapid development of electronic devices, such as semiconductor storage devices, there is a demand for a signal transmission circuit having plural or multi input terminals and a common output terminal to transmit an input signal without any distortion of the pulse profile and with satisfactory timing. This is particularly important for a multi-state read only memory (ROM), wherein the output voltage of a storage cell is compared with that of associated reference voltages to detect the level of the stored information. A more detailed description of the multi-state ROM is given in the following.
Recently, the demand for a storage device having a high capacity has been increasing. A character generator for KANJI, for example, requires a mask ROM of 1 to 2 M bits capacity. Accordingly, the direction of evolution for a semiconductor storage device has been to increase the number of storage elements per unit area on a semiconductor chip. For this purpose, various technologies for metal-insulator-semiconductor (MIS) devices such as metal-oxide-semiconductor (MOS) devices have been developed to minimize the dimension of the element devices such as MOS field effect transistors (FETs), conducting paths and the like, but there is a technical limitation. In order to overcome the limitation, multi-state storage cells have been used instead of the prior art binary storage cells, because a four state, quaternary, FET ROM, for example, is capable of storing twice as much information per unit area as a conventional binary ROM having the same number of storage devices per unit area on a semiconductor chip. The multi-state storage devices having multi-state FETs have been reported in Electronics, Oct. 9, 1980, page 39 by John G. Posa and Electronics, June 30, 1982, page 81 by J. Robert Lineback.
FIG. 1 is a partial circuit diagram showing how the quaternary storage information is detected. The FETs Q.sub.3 used for the four state storage cell MC (hereinafter "real cells") has one of four different conductances, gm.sub.0 to gm.sub.3, storing four different storage states, "0", "1", "2" and "3" respectively. These different gms are provided by varying the resistance of channels of the FETs Q.sub.3. There are several techniques for varying the conductance gm of an FET. Throughout this application, the different conductances for an FET are obtained by varying only the channel width W including the channel width W=0. Three reference voltages are created by reference FET Q.sub.R. One reference FET Q.sub.R forms one reference cell MC.sub.R. The conductances of the reference FETs Q.sub.R1 to Q.sub.R3 are respectively gm.sub.1 ', gm.sub.2 ' and gm.sub.3 ', wherein the gms are selected to be EQU gm.sub.0 &lt;gm.sub.1 '&lt;gm.sub.1 &lt;gm.sub.2 '&lt;gm.sub.2 &lt;gm.sub.3 '&lt;gm.sub.3
The corresponding channel widths W.sub.0 . . . of the real cell of FETs and W.sub.1 ' . . . of the reference of FETs satisfy the relation given by EQU W.sub.0 &lt;W.sub.1 '&lt;W.sub.1 &lt;W.sub.2 '&lt;W.sub.2 &lt;W.sub.3 '&lt;W.sub.3
FIG. 2 illustrates the relation between outputs 0 and channel widths W. Thus, the three outputs O.sub.1 ' to O.sub.3 ' of the reference cells Q.sub.R1 to Q.sub.R3 divide the output range from O.sub.0 to O.sub.3 into four portions.
When reading out the storage information, the real cell and the corresponding reference cells are selected by applying column selection signal V.sub.COL to the gate of the transfer FETs Q.sub.1 and Q.sub.2 to make the FETs conductive, and the Q.sub.3 and Q.sub.R are connected to the corresponding load resistors R.sub.1 and R.sub.2 through column lines. Then selection signals V.sub.WL and V.sub.RWL are applied to the gates of the FETs Q.sub.3 and Q.sub.R through the word line WL and the reference word line RWL respectively. Thus, at the nodes P.sub.1 and P.sub.2, the output O and O' of the cells are outputted. Further, the output of a real cell is compared simultaneously with the outputs from three reference cells Q.sub.R1 to Q.sub.R3 by three sense amplifiers SA.sub.1 to SA.sub.3 respectively (not shown), and a set of the three outputs of the sense amplifiers discriminate the level of the output O of the real cell.
The FETs used for real cells and reference cells have almost the same characteristics except for their conductance, namely, their channel width. As a result, the reference cells serve to provide reference outputs, namely, voltages, as long as the same gate voltage is applied to the gates of FETs for the real cells and reference cells at any instant of time. As stated above, the real cell and the corresponding reference cell are selected by a word line signal rising from the zero level, whereby the word line signal voltage is applied to the gates of the FETs of both cells in exactly the same way: maintaining the same change with time, namely, the same signal shape (a wave profile). Usually, the word lines are formed of poly-crystalline silicon, having a relatively high resistivity. As a result of a distributed parasitic capacitance along the word line, there is a significantly large time delay in the transmitting of signals at each storage cell along the word line. The time delay of the transmitting signal is inevitable. In order to eliminate the gap of the time delay between the respective word line signals at a reference cell and the corresponding real cell, both of which belong to the same column, each row of the reference cells has the same cell numbers and similar word line as those of the corresponding row of real cells. The row of reference cells including its word line is formed as if it is a duplicate of a row of real cells. With this configuration, almost the same time delay occurs at a real cell and the corresponding reference cell both of which are located in the same column. In addition, the profile of the word line signals are not the same, the reason for which will be described below. This is the reason why almost the similar circuit elements, word lines and cell FETs, have been formed in the prior art reference and dummy cell arrays in order to avoid the distortion, decay and time lag of the transmitting word line signals.
The almost double configuration of the prior art circuits occupies a large surface area of the substrate, adversely affecting the high packaging density of the storage device.
Of course, a fixed reference voltage, the power source voltage Vcc, for instance, can be applied to the gate of the FETs of the reference cells to create a fixed reference voltage. In this case, the rising word line signal should be applied to the gates of the FETs of the real cell until the signal reaches its final value, nearly Vcc, utilizing a strobe signal. This requires a relatively long time resulting in a longer access time.